Key Responsibilities:
- Architect, develop, and optimize low-latency FPGA-based solutions for high-frequency trading (stocks, options, futures, etc.).
- Collaborate closely with quantitative researchers and traders to implement and refine algorithmic strategies in hardware.
- Push the limits of parallel processing and real-time data pipelines to minimize execution times.
- Integrate FPGA systems with high-performance software components (C++, Python) for end-to-end trading infrastructure.
Technical Requirements:
Hardware Expertise:
- Proficiency in FPGA design and optimization (logic synthesis, pipelining, timing closure).
- Strong knowledge of digital logic design (clock domains, parallelism, low-level resource management).
- Experience with FPGA toolchains (Xilinx, Intel/Altera).
Software & Tooling:
- Hardware Description Languages (HDLs): Verilog, VHDL, SystemVerilog (for verification).
- High-Level Synthesis (HLS): C/C++ (Vitis HLS, Intel HLS) for FPGA algorithm development.
- Low-latency software integration: C++ (for system interaction), Python (for scripting/testing).
Preferred Skills (Not Mandatory):
- Familiarity with financial markets (trading concepts, market data protocols).
- Background in high-performance computing or network acceleration.
Why This Role?
- Work at the forefront of hardware-accelerated trading, where nanoseconds matter.
- Partner with top-tier quants and engineers to solve unique performance challenges.
- Opportunity to shape cutting-edge FPGA infrastructure in a fast-paced, intellectually rigorous environment.
Ideal Candidate Profile:
- Hybrid hardware/software mindset—able to bridge RTL design with system-level optimization.
- Passion for extreme performance tuning and solving problems at the hardware level.
- Strong problem-solving skills and adaptability in a high-stakes, collaborative setting.